1. Field of the Invention
The present invention relates to an electric power conversion apparatus, and more specifically to an electric power conversion apparatus having a circuit on a low side for performing a switching operation based on reference potential, and a circuit on a circuit on a high side for performing a switching operation based on floating reference potential.
2. Description of the Related Art
FIG. 1A shows an example of an electric power conversion apparatus for converting a direct current into a three-phase alternating current in the conventional technology.
In FIG. 1A, semiconductor switches Q11 through Q13 and semiconductor switches Q21 through Q23 are configured by, for example, an IGBT (insulated gate bipolar transistor), perform a switching operation depending on the control of drive circuits 11 through 13 and drive circuits 21 through 23, convert a direct current voltage into a three-phase alternating current, and provide it for a three-phase motor 36.
With the configuration the semiconductor switches Q21 through Q23 and the drive circuits 21 through 23 perform a switching process using a ground level as reference potential. Therefore, they are referred to as a circuit on a low side circuit. On the other hand, since the semiconductor switches Q11 through Q13 and the drive circuits 11 through 13 perform a switching operation using the potential at terminal U, V, and W (fluctuating potential) as reference potential, they are referred to as a circuit on a high side. In the description below, the reference potential of the circuit on the low side is simply-called xe2x80x98reference potentialxe2x80x99 while the reference potential of the circuit on the high side is called xe2x80x98floating reference potentialxe2x80x99.
A control unit 30 is configured by, for example, a CPU (central processing unit), ROM (read-only memory), RAM (random access memory), etc., controls each drive circuit through an I/F (interface) 35, and stops the operations of each drive unit when an alarm signal informing that an abnormal condition occurs is issued from each drive circuit.
The I/F 35 serves as an interface for information with the circuit on the low side and the control unit 30, and also serves as an interface for information with the circuit on the high side and the control unit 30 (described later).
FIG. 1B shows an example of a detailed configuration of the drive circuits 11 and 21 shown in FIG. 1A and the peripheral units.
As shown in FIG. 1B, the drive circuit 11 includes a power supply monitor unit 11a, an abnormal condition detection unit 11b, an I/F 11c, and a driver 11d. The drive circuit 21 is similarly configured.
The power supply monitor unit 11a determines whether or not the power supply voltage provided for the drive circuit 11 is in a normal range, and notifies the control unit 30 of the determination result through the I/F 11c if it determines an abnormal condition.
The abnormal condition detection unit 11b monitors the electric current flowing through the semiconductor switch Q11, and the temperature of the semiconductor switch Q11, and notifies the control unit 30 through the I/F 11c when an excess current flows through the semiconductor switch Q11, or when the semiconductor switch Q11 is overheating.
The I/F 11c cooperates with the I/F 35 for the consistency of physical properties so that information can be transmitted and received between the drive circuit 11 whose reference potential is not constant (that is, fluctuates depending on the status of an output) and the control unit 30 whose ground level is reference potential.
The driver 11d drives the semiconductor switch Q11 according to the control signal provided from the control unit 30 through the I/F 11c. 
The drive circuit 21 has the similar configuration with the exception of a power supply monitor unit 21a. That is, since the drive circuits 11 through 13 have different reference potential, it is necessary to individually detect the power supply to be provided for each drive circuit. On the other hand, all of the drive circuits 21 through 23 have the ground level, only one power supply monitor unit has to be provided for one of the drive circuits 21 through 23. In this example, only the drive circuit 21 is provided with the power supply monitor unit 21a. 
FIG. 1C shows the details of the portion for transmitting alarm signals of the I/F 11c and the I/F 35.
As shown in FIG. 1C, the portion for transmitting an alarm signal of the I/F 11c includes a P-channel MOS type FET 11ca, an inverter 11cb, and a power source 11cc. The power source 11cc is equivalent to an externally provided power source.
The portion for transmitting an alarm signal of the I/F 35 includes a power supply 35a, an inverter 35b, and a resistor 35c. 
FIG. 1D shows in detail the circuit of the portion for transmitting control signals of the I/F 11c and the I/F 35.
As shown in FIG. 1D, the portion for transmitting a control signal of the drive circuit 11 includes a resistor 42 and an inverter 43. The resistor 42 is connected to the plus terminal of the I/F 11c, and the output of the inverter 43 is connected to the driver 11d. 
The portion for transmitting a control signal of the I/F 35 includes an inverter 40, and an N-channel MOS type FET 41. The input of the inverter 40 is connected to the control unit 30, and the output is connected to the gate of the N-channel MOS type FET 41. The source of the N-channel MOS type FET 41 is grounded, and the drain is connected to the input terminal of the inverter 43.
Described below are the operations according to the above mentioned conventional technology. In the following explanation, the operations of the portion for transmitting the control signal shown in FIG. 1D are described first, and then the operations of the portion for transmitting the alarm signal shown in FIG. 1C are described.
First, the operation of the portion for transmitting a control signal is described below by referring to FIG. 1D.
When a control signal is issued from the control unit 30 to the inverter 40, the N-channel MOS type FET 41 enters an ON or OF state depending on the output of the inverter 40. When the output from the control unit 30 indicates the H state, the output from the inverter 40 indicates the L state, and the N-channel MOS type FET 41 enters the OFF state. If the N-channel MOS type FET 41 enters the OFF state, the input of the inverter 43 indicates the H state. Therefore, the output of the inverter 43 indicates the L state, and the driver 11d drives the semiconductor switch Q11 depending on the state and drives the semiconductor switch Q11 (for example, sets the semiconductor switch Q11 in the OFF state)
On the other hand, when the output from the control unit 30 indicates the L state, the output of the inverter 40 indicates the H state, and the N-channel MOS type FET 41 enters the ON state. When the N-channel MOS type FET 41 enters the ON state, the input of the inverter 43 indicates the L state. Therefore, the output of the inverter 43 indicates the H state, and the driver 11d drives the semiconductor switch Q11 depending on the state (for example, sets the semiconductor switch Q11 in the ON state).
In the above mentioned process, the semiconductor switch Q11 can be appropriately controlled. Other semiconductor switches can also be switched in the similar operations.
The circuit shown in FIG. 1D can be replaced with the circuit shown in FIG. 1E.
In this example, a source grounding circuit includes N-channel MOS type FETs 45 and 46, and load resistors 47 and 48. The output of the load resistors 47 and 48 are respectively input to the S terminal and the R terminal of a flipflop 49. The output of the flipflop 49 is input to the driver 11d, and an on-pulse and an off-pulse are respectively provided for the N-channel MOS type FETs 45 and 46.
When the drain potential enters the H state by the on-pulse input to the N-channel MOS type FET 45, the flipflop 49 latches it, sets the output in the H state, and resets the output in the L state depending on the off-pulse. The semiconductor switch Q11 can be driven by repeating the operations.
Then, by referring to FIG. 1C, the operations of the portion for transmitting an alarm signal are described below.
When the power supply monitor unit 11a or the abnormal condition detection unit 11b detects an abnormal condition in the power supply or the semiconductor switch Q11, then an alarm signal is set in the H state, and is input to the inverter 11cb. 
The inverter 11cb inverts the state of the alarm signal, and provides it for the P-channel MOS type FET 11ca. Since the input alarm signal is in the H state, the output of the inverter 11cb is in the L state. As a result, the P-channel MOS type FET 11ca enters the ON state.
When the P-channel MOS type FET 11ca enters the ON state, an electric current flows from the power source 11cc to the resistor 35c. Therefore, a predetermined voltage is generated on either end of the resistor 35c. 
Since the inverter 35b inverts the voltage generated in the resistor 35c and outputs it as an alarm signal, the alarm signal, which is an output of the inverter 35b, enters the L state when the P-channel MOS type FET 11ca enters the ON state.
When the alarm signal output from the inverter 35b enters the L state, the control unit 30 assumes that an abnormal condition occurs on the high side, and stops the operations of all drive circuits. Similar processes are performed on other drive circuits.
When an abnormal condition arises on the high side during the above mentioned processes, the operations of all drive circuits stop to prevent the semiconductor switches from being damaged.
In the above mentioned conventional technology, the reference potential of the drive circuits 11 through 13 is the potential at an output point as described above. Therefore, a voltage substantially equal to the direct current voltage to be switched can be applied to the P-channel MOS type FET 11ca. 
As a result, it is necessary to use an element having a high withstand voltage as the P-channel MOS type FET 11ca. However, since a P-channel MOS type FET having a high withstand voltage is normally expensive, the production cost of an apparatus is considerably high. Furthermore, since a P-channel MOS type FET 11ca having a large withstand voltage is large in size, the entire apparatus can be very large.
The present invention has been developed to solve the above mentioned problems, and aims at providing an inexpensive and smaller electric power conversion apparatus.
The electric power conversion apparatus according to the present invention comprises a circuit on the low side for performing a switching operation based on the reference potential, and a circuit on the high side for performing a switching operation based on the floating reference potential. With the configuration, the difference between the reference potential and the floating reference potential fluctuates. The high side comprises a detection unit and a signal generation unit, and the low side comprises a reception unit and a control unit.
The detection unit detects the state of an operation of the circuit on the high side.
The signal generation unit generates a signal based on the detection result of the detection unit.
The reception unit receives a signal generated by the signal generation unit.
The control unit controls the above mentioned circuits on the low and high sides according to the signal received by the reception unit.
The signal generation unit and the reception unit are connected to each other using a directional element with which the connection or disconnection state is determined based on the transmission direction of a signal.